CSE211
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Course:CSE306::COMPUTER NETWORKS

Time Allowed: 03:00 hrs Max. Marks: 100

1. This paper contains 6 questions divided in two parts.

2. All questions are compulsory.

3. The marks assigned to each questions are shown at the end of the question in square brackets.

4. Attempt either (a) OR (b) from each question of Part B.

5. Answer all the questions in serial order.

6. Do not write anything on the question paper except your registration number at the designated space.

PART A

Q1.a) What do mean by clocked sequential circuits?

b) In concern to excitation table, what will be the value for S and R if the present state (Q(t)) and next state (Q(t+1)) both are equal to 1.

c) Explain briefly the decode stage of instruction cycle.

d) Explain CLE, BUN and OUT instructions.

e) What is the difference between RISC and CISC?

f f) What do you mean by operation code?

g) How overflow condition is checked in division algorithm?

h) Draw hardware for signed 2’s complement addition and subtraction.

i i) What is the difference between primary and secondary memory?

j) What is content addressable memory (CAM) ?

PART B

Q2.a) What do you mean by clocked sequential circuits?

b) The contents of Program counter in the basic computer is 3AF (all in hexadecimal). The contents of 3AF is 932E. The content of 32E is 09AC. Discuss Fetch and Decode phase of instruction using above mentioned values and diagram.

Q3.a) Explain various data transfer and manipulation instructions?

b) What do you mean by RISC & CISC? Explain RISC and CISC characteristics properly.

Q4.a) Draw the flowchart for divide operation and explain the term DVF.

b) Explain the hardware implementation of add and subtract operation also draw the flowchart for this.

Q5.a) Explain the model of Data Transfer between the central computer (CPU or Memory) and peripherals in which peripheral devices after granting their valid request by the CPU can access memory directly without any further intervention of CPU. Draw suitable diagrams to justify your answer.

b) In case of Programmed I/O mode of transfer CPU is wasting lot of time while checking the flag of status register instead of doing other useful processing task. Can we further improve this mechanism? If yes then provide alternatives to improve this model of transfer.

Q6.a) What is the benefit of using the microprocessor systems in contrast of single processor system? Write the characteristics of multiprocessor systems .

b) What are interconnection structures? Explain in detail the multistage switching network and hypercube system by using suitable diagrams.

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